1. Technical Field
This invention relates to performance monitoring within a speculative microprocessor, more particularly, to maintaining a correct value in a performance monitor counter, and still more particularly to using a rewind register to maintain a correct value in a performance monitor counter within a speculative microprocessor.
2. Description of the Related Art
Many modem microprocessors include a Performance Monitor Unit (PMU). The PMU contains one ore more counters (PMCs) that accumulate the occurrence of internal events that impact or are related to the performance of a microprocessor. For example, a PMU may monitor processor cycles, instructions completed, or delay cycles executing a load from memory. These statistics are useful in optimizing the architecture of a microprocessor and the instructions executed by a microprocessor.
Advances in computer architecture have complicated monitoring events in microprocessors. Specifically, modern processors use speculative execution to improve performance. When a non-speculative processor executes a conditional branch instruction it must first have the results of the condition available before the direction of the branch may be determined. Speculative processors predict, or speculate, on the direction of the branch. If, after the operands are available and the condition may be evaluated, the processor determines if the prediction was correct. If the processor predicted correctly then execution continues. Otherwise, the processor flushes the mispredicted instructions and beings fetching instructions along the correct path.
Similarly, counters within the PMU will contain incorrect values and will need to be adjusted in the event of a misprediction. However, there is no solution in the prior art for correctly resetting PMCs in the event of a branch misprediction. Consequently, the values stored in the PMCs may be incorrect.
Therefore, there is a need for a new and improved method and system for adjusting a counter in a performance monitor unit within a speculative microprocessor in the event of a branch misprediction.